1. Field of the Invention
The present invention relates to a gate drive circuit with a feedback-controlled active resistance. More specifically, the invention relates to a gate drive circuit that modifies the turn-on and turn-off steps in a drive signal to reduce di/dt and therefore electromagnetic interference, particularly for insulated gate devices.
2. Brief Description of the Related Art
Power switches used in power converters are usually insulated gate devices such as insulated gate bipolar transistors (IGBTs). These devices need a special control circuit to provide signals to their gates, usually called a gate driver. Typically, a gate driver has a simple structure that allows application of either positive or negative voltage on the gate.
A. Switching Waveforms
FIG. 1 shows typical switching waveforms that occur at turn-on in an insulated gate device. The waveforms illustrate the slopes of the collector voltage and current and the time intervals on which di/dt (xcex41) and dv/dt (xcex42) are defined.
During the xcex40 time interval, the gate voltage (VG) rises to the threshold level and the collector current IC) equals Idss up to hundreds of xcexcA. The slope of the gate voltage is given by the input capacitance that is now equal to Ciss for the specific device.
During the xcex41 time interval, IC starts to increase and reaches its maximum equal to the load current. The slope at which IC increases depends on the gate resistance (RGON) and IGBT characteristics. An approximate equation is:                                           (                                          ⅆ                                  i                  d                                                            ⅆ                t                                      )                    on                ≈                                            V              G              +                        -                                          V                GE                            ⁡                              (                                                      I                    L                                    +                                      I                    RM                                                  )                                                                        (                                                                    C                    ies                                    ·                                      R                    GON                                                                    g                  fe                                            )                        +                          L              E                                                          (        1        )            
During the xcex42 time interval, the Miller effect interval keeps the gate voltage at a constant level while the collector-emitter voltage decreases from the DC bus level. The slope of this variation also depends on the gate resistance and is given by an approximate relationship:                                           (                                          ⅆ                v                                            ⅆ                t                                      )                    on                ≈                                            V              G              +                        -                                          V                GE                            ⁡                              (                                  I                  C                                )                                                                        R              Gon                        ·                          C              GC                                                          (        2        )            
During the xcex43 time interval, the gate voltage again increases to the control voltage.
FIG. 2 shows typical switching waveforms that occur at turn-off. As above, the waveforms illustrate current and voltage slopes.
During the xcex40xe2x80x2 time interval, the gate voltage (VG) decreases up to the Miller effect level.
During the xcex41xe2x80x2 time interval, the collector-emitter voltage increases to the DC bus voltage and the slope is defined by the gate resistance and the IGBT""s characteristics. The slope is given by another approximate relationship:                                           (                                          ⅆ                v                                            ⅆ                t                                      )                    off                ≈                                                            V                GE                            ⁡                              (                                  I                  L                                )                                      -                          V              Gmin                                                          R              Goff                        ·                          C              GC                                                          (        3        )            
During the xcex42xe2x80x2 time interval, the collector current decreases and the slope is approximated by an equation similar to equation (1) above.
B. Influence on EMI
The design of a gate driver has an important influence on the EMI that is generated. It can influence both major types of electromagnetic interference:
differential mode currents flowing into connecting lines due to the IGBT""s/diode""s switching current (di/dt); and
common mode interference produced by the high rate of change of the switching voltage (dv/dt) and parasitic capacitances to the ground or connecting lines.
The level of radiated or conducted EMI depends not only on the gate resistance but also in the converter system parasitics and the pulse width modulation (PWM) method being used.
To control EMI emission, it is necessary to control the switching rate and the voltage and current waveforms based on the values of gate resistance and the switching off voltage (xe2x88x9215V or 0V). For a typical inverter, problems with differential mode EMI constrain the designer to reduce di/dt. The dv/dt levels are imposed by output waveform harmonic considerations and cannot be reduced very much. The harmonic content of the output voltage and switching loss considerations make it impossible to slow down the switching speed. On the contrary, fast dv/dt inverters are sometimes desirable. Recently developed approaches make it possible to control di/dt without affecting dv/dt capability by injecting additional gate current when necessary. Usually designers use such controls to reduce turn-on di/dt and to reduce overvoltage at turn-off.
Gate resistor design is subject to other constraints such as switching power losses, diode recovery transients, and the need to avoid cross-conduction. As used herein, the term xe2x80x9cgate resistorxe2x80x9d refers to a gate resistor equivalent that can be implemented by various means including, but not limited to, a conventional passive resistor.
Circuit 20 in FIG. 3 illustrates a simplified approach to controlling (di/dt) by controlling gate current with a proposed feedback loop from the emitter of IGBT 22 to the output of gate driver 24. This approach is described in detail in Gerster, C., and Hofer-Noser, P., xe2x80x9cGate-controlled dv/dt and di/dt Limitation in High-Power IGBT Converters,xe2x80x9d EPE Journal, Vol. 5, No. 3/4, January 1996.
There are numerous obvious constraints on implementing this approach, and a number of different solutions have been proposed by those seeking the best implementation. Two main constraints preventing easy implementation are:
a fast event time scale that allows very little delay within the circuit; and
feedback dependence on IGBT parameters.
The literature presents many solutions, based on different understandings of the problem. EMI generation is not simple to quantify, and its real sources and their weights in overall EMI generation are not easy to identify. Every possible parasitic in the inverter setup has an influence, and both di/dt and dv/dt contribute through the parasitics, during both turn-on and turn-off.
C. Solution I
Musumeci, S., Raciti, A., Testa, A., Galluzzo, A., and Melito, M., xe2x80x9cSwitching Behavior Improvement of Insulated Gate-Controlled Devicesxe2x80x9d, IEEE Trans. On PE, Vol. 12, No. 4, July 1997, pp. 645-653, propose a solution that shapes gate current during the Miller effect interval. This achieves independent control of the slopes of collector voltage and current. The proposed solution, illustrated by circuit 30 in FIG. 4, supplies pulses of gate current to IGBT 32 at the beginning of the Miller effect interval, speeding up the variation of the collector voltage without changing the slope of the collector current. Problems with this solution relate to detection of the Miller effect zone by sensor 34 and enabling a suitable current pulse generator 36 synchronous with the moment the zone is reached. This is very important to minimize power losses. Maximum loss reduction has been demonstrated by inserting gate current pulses within 20% delay after sensing the Miller effect zone. This can be achieved by an optimal gate-emitter voltage, a strong constant current pulse from generator 36 at turn-on, and a constant current sink 38 at turn-off.
Among the most sensitive parts of this design is implementation of enable modules 40 and 42. The simplest solution is a high gain amplifier that converts information from sensor 34 into signals that, for example, cause generator 36 to provide gate current pulses. The main drawbacks of this solution relate to dependence on circuit speed and to noise. A more complex solution employs a phase locked loop (PLL) circuit to synchronize current pulses on a next-pulse basis. The PLL circuit works to compensate any processing delay. Any phase difference detected by the phase comparator modifies time delay between command signal and gate current pulses, adjusting the phase difference on the next switching.
FIGS. 5 and 6 show examples of relationships between VGE in IGBT 32 and enable signals to current pulse generator 36 and current sink 38, respectively.
D. Solution II
Takizawi, S., Igarashi, S., and Kuroki, K., xe2x80x9cA New di/dt Control Gate Drive Circuit for IGBTs to Reduce EMI Noise and Switching Lossesxe2x80x9d, IEEE 1998, pp. 1443-1449, propose another solution, a xe2x80x9cdi/dt suppressorxe2x80x9d, that limits di/dt at turn-on if collector currents are low. This solution can also be described as improving the diode dv/dt, and hence reducing common mode EMI. At low collector currents, reverse recovery dv/dt of a diode is large and the EMI level is high. The authors state that, for a given gate resistance, EMI is larger at low collector currents than at higher currents. Moreover, different approaches are proposed for turn-on and turn-off.
At turn-on, suppression circuit 70 in FIG. 7 is enabled at small currents through IGBT 72 and limits di/dt. As noted above, diode reverse recovery dv/dt, and therefore EMI noise, is larger at small currents than at large load currents. Therefore, detector 74 receives collector current IC and provides a high signal when IC rises. Store 76 provides a signal with information about the last measured load current, providing a high signal when the last load current was small. If both signals are high, AND gate 78 closes switch 80, connecting resistance 82 in parallel with resistance 84 to reduce di/dt at small load currents and also reduce diode dv/dt. The relationship between VGE, IC, and the output signal from AND gate 78 are shown in FIG. 8.
At turn-off, collector-emitter voltage rises to a level that is directly proportional to the magnitude of di/dt and also depends on the level of commutated phase current. Suppression circuit 90 in FIG. 9 limits di/dt when collector current for IGBT 92 is falling and load current would be high. Detector 94 receives collector current IC and provides a high signal when IC falls. In parallel, detector 96 measures load current and provides a high signal when load current is large. If either signal is low, NAND gate 98 closes switch 100, connecting resistance 102 in parallel with capacitance 104 to reduce di/dt at small load currents. The relationship between VGE, IC, and the output signal from NAND gate 98 are shown in FIG. 10.
E. Solution III
A possible solution based on a three stage active gate driver implemented with a closed loop is disclosed in U.S. Pat. No. 6,208,185.
FIG. 11 shows the three stages at turn on, which can be described as follows:
Stage I: This stage minimizes delay time by rapidly charging the IGBT gate with a large gate current.
Stage II: Turn-on di/dt is controlled by a reduced rate of charging the IGBT gate. Injected current is reduced to minimize over-voltage across the complementary switch caused by free-wheeling diode snap-off and the EMI generated by ringing during the reverse recovery transient.
Stage III: The IGBT gate is rapidly charged to reduce tail voltage and decrease power losses.
FIG. 12 shows the three stages at turn off, which can be described as follows:
Stage I: The gate-emitter capacitor discharges rapidly until the collector voltage begins to rise.
Stage II: Gate current is reduced and this results in lower turn-off di/dt and reduced over-voltage during turn-off. This stage continues through the rising period of collector voltage and the falling period of collector current.
Stage III: This stage starts when the collector current stops falling.
FIG. 13 shows circuit 120, an implementation in which rail-to-rail MOSFET transistors 122 and 124, respectively labeled B1 and B2, help provide the high current needed in Stages I and III. Resistors 126 and 128, respectively labeled R1 and R2, limit peak gate current during Stages I and III. Bipolar transistors 130 and 132, respectively labeled M1 and M2, allow precise gate current control during Stage II of the active switching transient.
Table I shows in greater detail how the transistors are controlled during turn-on and turn-off, and the comments indicate the roles played by R1 and R2.
F. Solution IV
The IR3210, a product of the assignee, International Rectifier Corporation, employs a simplified solution that is partly closed loop and takes advantage of predefined current shapes. In this solution, current profiles are programmable through external resistors. FIGS. 14 and 15 show the relationships between VGE and gate current waveforms during turn-on and turn-off; respectively.
It is desirable to have a control circuit for an insulated gate device that overcomes problems with the above solutions, has low response time, and is simple to implement.
The present invention provides a new gate control technique for gated devices such as IGBTs. The new technique employs an active resistance between input and output leads. The active resistance is controlled in response to a feedback signal that includes information about the output drive signal at the output lead, to provide an output drive signal that is a modified version of the input drive signal.
The new technique can be implemented to obtain optimal di/dt while maintaining dv/dt performance and limiting EMI generation. The new technique is also advantageous because the active resistance can be implemented in a device with a very fast response time, such as a MOSFET resistor. This provides a very simple gate control circuit that can be implemented in an integrated circuit (IC) with an output pin that can be connected directly to the gate of an IGBT, without feedback from the power stage. The feedback for the active gate control is obtained from the RC circuit present on the gate. A gate control circuit can be implemented with fewer components than previous solutions, even those requiring only two external components. Because the active resistance can be implemented in a MOSFET, the new technique can be redesigned. when changing to a new IC technology without modifying the central concept. Further, the active resistance is compatible with the function of desaturation (Desat) protection; in other words, the IC""s output stage can perform multiple functions while being controlled by an active resistance.
The new technique can be implemented in a method in which an input drive signal is received at an input lead and, in response to the input drive signal and a feedback signal, an output drive signal for a gated device, such as an IGBT, is provided at an output lead. The feedback signal includes information about the output drive signal. In the method, an active resistance between the input and output leads is controlled in response to the feedback signal so that the output drive signal is a modified version of the input drive signal.
The input drive signal can include turn-on and turn-off steps and the output drive signal can include turn-on and turn-off transitions that are modified forms of the turn-on and turn-off steps. The transition can, for example, include an interval during which the active resistance is greater than zero to reduce peak voltage, another interval during which the active resistance is approximately zero to allow a large gate current, and yet another interval during which the active resistance is greater than zero to limit gate current.
The new technique can be implemented in a gate control circuit that receives input drive signals and, in response, provides output drive signals to the gate of an insulated gate device. The gate control circuit has input and output leads for receiving input drive signals and for providing output drive signals to the device""s gate, respectively. Sensing circuitry provides a feedback signal that includes information about an output drive signal provided in response to an input drive signal. Active resistance circuitry provides an active resistance between the input and output leads and responds to the feedback signal by controlling the active resistance so that the output drive signal is a modified version of the input drive signal.
The input drive signal can include turn-on and turn-off steps, as above, and the sensing circuitry can provide a turn-on feedback signal when a turn-on step occurs and a turn-off feedback signal when a turn-off step occurs. The active resistance circuitry can include turn-on circuitry and turn-off circuitry. The turn-on circuitry responds to the turn-on feedback signal by controlling the active resistance to provide a turn-on transition. Similarly, the turn-off circuitry responds to the turn-off feedback signal by controlling the active resistance to provide a turn-off transition. The turn-on and turn-off transitions can reduce di/dt for the insulated gate device.
The active resistance circuitry can include an active resistance device that has a gate lead for receiving a control signal and a channel connected in series between the input and output leads. Resistance of the channel is controlled by the control signal, which can be provided by control signal circuitry in response to the feedback signal. The active resistance device can, for example, be a MOSFET resistor. The feedback signals can, for example, indicate voltage at the output lead and the control signal circuitry can include first stage circuitry, such as a current mirror, for inverting the feedback signals and second stage circuitry for applying the inverted feedback signals to the gate lead of the active device, such as through high and low side transistors.
An integrated circuit can include the gate control circuit. The insulated gate device can be an IGBT, and the integrated circuit can also include an output pin for connecting directly to the gate of the IGBT. The output pin can provide the output drive signal to the IGBT""s gate.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.